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| SSM9973GH,J N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low gate-charge Simple drive requirement Fast switching G D BV DSS R DS(ON) ID 60V 80m 14A S Description The SSM9973GH is in a TO-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. The through-hole version, the SSM9973GJ in TO-251, is available for low-footprint vertical mounting. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. GD S TO-252 (H) Pb-free lead finish (second-level interconnect) G D S TO-251 (J) Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=100C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current 1 Rating 60 20 14 9 40 27 0.22 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 4.5 110 Unit C/W C/W 2/16/2005 Rev.2.2 www.SiliconStandard.com 1 of 5 SSM9973GH,J Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance2 Test Conditions VGS=0V, ID=250uA Min. 60 1 Typ. 0.05 8.6 8 3 4 7 15 16 3 720 77 45 Max. Units 80 100 3 1 25 100 13 1150 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA VGS=10V, ID=9A VGS=4.5V, ID=6A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=150 C) o o VDS=VGS, ID=250uA VDS=10V, ID=9A VDS=60V, VGS=0V VDS=48V ,VGS=0V VGS= 20V ID=9A VDS=48V VGS=4.5V VDS=30V ID=9A RG=3.3 ,VGS=10V RD=3.3 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 Test Conditions IS=14A, VGS=0V IS=9A, VGS=0V, dI/dt=100A/s Min. - Typ. 28 27 Max. Units 1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 2/16/2005 Rev.2.2 www.SiliconStandard.com 2 of 5 SSM9973GH,J 45 32 40 T C =25 C o 35 ID , Drain Current (A) 30 ID , Drain Current (A) 10V 7.0V 5.0V 4.5V 28 T C =150 o C 24 10V 7.0V 5.0V 4.5V 20 25 16 20 12 15 8 V G =3.0V 10 V G =3.0V 4 5 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 90 2.5 ID=9A 85 I D =9A 2.0 T C =25 C Normalized RDS(ON) o V G =10V RDS(ON) (m ) 80 1.5 75 1.0 70 0.5 65 0.0 3 5 7 9 11 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2.5 14 12 2 10 8 IS(A) o T j =150 C 6 T j =25 o C VGS(th) (V) 1.4 1.5 1 4 0.5 2 0 0 0.2 0.4 0.6 0.8 1 1.2 0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j ,Junction Temperature ( C) o Fig 5. Forward Characteristic of the Reverse Diode Fig 6. Gate Threshold Voltage vs. Junction Temperature 2/16/2005 Rev.2.2 www.SiliconStandard.com 3 of 5 SSM9973GH,J f=1.0MHz 12 10000 ID=9A VGS , Gate to Source Voltage (V) 10 8 6 4 C (pF) V DS =48V V DS =38V V DS =30V 1000 Ciss 100 Coss Crss 2 0 10 0 4 8 12 16 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (R thjc) Duty factor=0.5 1ms 10 0.2 ID (A) 0.1 0.1 0.05 10ms 1 PDM 0.02 T C =25 o C Single Pulse 0.1 0.1 1 10 100ms 1s DC t T Single Pulse 0.01 Duty factor = t/T Peak Tj = PDM x Rthjc + TC 0.01 100 1000 0.00001 0.0001 0.001 0.01 0.1 1 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 2/16/2005 Rev.2.2 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9973GH,J Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 2/16/2005 Rev.2.2 www.SiliconStandard.com 5 of 5 |
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